Field of the Invention
Embodiments of the present invention relate generally to computer science and, more specifically, to opportunistic migration of memory pages in a unified virtual memory system.
Description of the Related Art
Multiprocessor systems typically include a main processor with a system memory that includes data and instructions for the main processor. Portions of this system memory may also be accessible to one or more auxiliary processors, where auxiliary processors may be used to offload certain processing tasks from the main processor. Such a portion of system memory is called a shared memory. The main processor may generate instructions and data directed to an auxiliary processor and store the instructions and data in shared memory. The auxiliary processor may then retrieve the instructions and data from shared memory, perform the operations indicated by the instructions, and store resulting data back to shared memory. The main processor then retrieves the resulting data from the share memory.
One drawback of this approach is that memory access operations generated by the auxiliary processors and directed to shared memory may have relatively high latency, as compared with memory access operations generated by the auxiliary processors that are directed to local memory. As such, the advantage of offloading tasks from the main processor to the auxiliary processor can be reduced.
One possible solution to this drawback is to copy the instructions and data from shared memory into the local memory of the auxiliary processor. The auxiliary processor then retrieves instructions and data from relatively low latency local memory rather than relatively high latency shared memory. One drawback to this type of solution is that the execution of the instructions by the auxiliary processor is delayed until at least some of the shared memory pages that include the needed instructions and data are transferred from the shared memory to the local memory of the auxiliary processor.
Accordingly, what is needed in the art is a more effective way to transition memory pages between different processors in a multi-processor architecture.